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data sheet ?2007-2009 cadeka microcircuits llc www.cadeka.com c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a c omlinear ? CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers f e a t u r e s n unity gain stable n 100db voltage gain n 550khz unity gain bandwidth n 0.5ma supply current n 20na input bias current n 2mv input offset voltage n 3v to 36v single supply voltage range n 1.5v to 18v dual supply voltage range n input common mode voltage range includes ground n 0v to v s -1.5v output voltage swing n clc2050: improved replacement for industry standard lm358 n clc4050: improved replacement for industry standard lm324 n CLC1050: pb-free sot23-5 n clc2050: pb-free soic-8 n clc4050: pb-free soic-14 a p p l i c a t i o n s n battery charger n active filters n transducer amplifers n general purpose controllers n general purpose instruments general description the comlinear CLC1050 (single), clc2050 (dual), and clc4050 (quad) are voltage feedback amplifers that are internally frequency compensated to provide unity gain stability. at unity gain (g=1), these amplifers offer 550khz of bandwidth. they consume only 0.5ma of supply current over the entire power supply operating range. the CLC1050, clc2050, and clc4050 are specifcally designed to operate from single or dual supply voltages. the comlinear CLC1050, clc2050, and clc4050 offer a common mode voltage range that includes ground and a wide output voltage swing. the combination of low-power, high supply voltage range, and low supply current make these amplifers well suited for many general purpose applications and as alternatives to several industry standard amplifers on the market today. typical application - voltage controlled oscillator (vco) ordering information part number package pb-free rohs compliant operating temperature range packaging method CLC1050ist5x sot23-5 yes yes -40c to +85c reel clc2050iso8x soic-8 yes yes -40c to +85c reel clc4050iso14x soic-14 yes yes -40c to +85c reel moisture sensitivity level for all parts is msl-1. v cc v+/2 r 10 0 k 51k 51k 0.05 f output 2 51 k r/2 50k ? + 1/ 2 clcx050 ? + 1/ 2 clcx050 output 1 100k 10k a m p l i f y t h e h u m a n e x p e r i e n c e
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 2 CLC1050 pin assignments pin no. pin name description 1 out output 2 -v s negative supply 3 +in positive input 4 -in negative input 5 +v s positive supply clc2050 pin confguration pin no. pin name description 1 out1 output, channel 1 2 -in1 negative input, channel 1 3 +in1 positive input, channel 1 4 -v s negative supply 5 +in2 positive input, channel 2 6 -in2 negative input, channel 2 7 out2 output, channel 2 8 +v s positive supply clc4050 pin confguration pin no. pin name description 1 out1 output, channel 1 2 -in1 negative input, channel 1 3 +in1 positive input, channel 1 4 +v s positive supply 5 +in2 positive input, channel 2 6 -in2 negative input, channel 2 7 out2 output, channel 2 8 out3 output, channel 3 9 -in3 negative input, channel 3 10 +in3 positive input, channel 3 11 -v s negative supply 12 +in4 positive input, channel 4 13 -in4 negative input, channel 4 14 out4 output, channel 4 CLC1050 pin confguration clc2050 pin confguration 2 3 5 4 +in +v s -in 1 -v s out - + 2 3 4 5 6 7 8 out2 +in1 -in2 +in2 1 -in1 out1 -v s +v s clc4050 pin confguration 2 3 4 11 12 13 14 -in4 +in1 out4 +in4 1 -in1 out1 5 6 7 out2 -in2 +in2 8 9 10 +in3 -in3 out3 +vs -vs
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 3 absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper de - vice function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit supply voltage 0 40 v differential input voltage 40 v input voltage -0.3 40 v power dissipation (t a = 25c) - soic-8 550 mw power dissipation (t a = 25c) - soic-14 800 mw reliability information parameter min typ max unit junction temperature 150 c storage temperature range -65 150 c lead temperature (soldering, 10s) 260 c package thermal resistance sot23-5 221 c/w soic-8 100 c/w soic-14 88 c/w notes: package thermal resistance ( q ja ), jdec standard, multi-layer test boards, still air. recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c supply voltage range 3 (1.5) 36 (18) v
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 4 electrical characteristics t a = 25c (if bold , t a = -40 to +85c), v s = +5v, -v s = gnd, r f = r g =2k, r l = 2k to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units frequency domain response ugbw ss unity gain bandwidth g = +1, v out = 0.2v pp , v s = 5v 330 khz g = +1, v out = 0.2v pp , v s = 30v 550 khz bw ss -3db bandwidth g = +2, v out = 0.2v pp , v s = 5v 300 khz g = +1, v out = 0.2v pp , v s = 30v 422 khz bw ls large signal bandwidth g = +2, v out = 1v pp , v s = 5v 107 khz g = +2, v out = 2v pp , v s = 30v 76 khz time domain response t r , t f rise and fall time v out = 1v step; (10% to 90%), v s = 5v 4 s v out = 2v step; (10% to 90%), v s = 30v 5.6 s os overshoot v out = 0.2v step 1 % sr slew rate 1v step, v s = 5v 200 v/ms 4v step, v s = 30v 285 v/ms distortion/noise response thd total harmonic distortion v out = 2v pp , f = 1khz, g = 20db, c l = 100pf, v s = 30v 0.015 % e n input voltage noise > 10khz, v s = 5v 45 nv/hz > 10khz, v s = 30v 40 nv/hz x talk crosstalk channel-to-channel, 1khz to 20khz 120 db dc performance v io input offset voltage (1) v out = 1.4v, r s = 0, v s = 5v to 30v 2 5 mv 7 mv dv io average drift 7 v/c i b input bias current (1) v cm = 0v 20 100 na 200 na i os input offset current (1) v cm = 0v 5 30 na 100 na psrr power supply rejection ratio (1) dc, v s = 5v to 30v 70 100 db 60 db a ol open-loop gain (1) +v s = 15v, r l = 2k, v out = 1v to 11v 85 100 db 80 db i s supply current, CLC1050 (1) r l = , v s = 30v 0.65 1.5 ma r l = , v s = 5v 0.45 1.0 ma supply current, clc2050 (1) r l = , v s = 30v 0.7 2.0 ma r l = , v s = 5v 0.5 1.2 ma supply current, clc4050 (1) r l = , v s = 30v 1.0 3.0 ma r l = , v s = 5v 0.7 1.2 ma input characteristics cmir common mode input range (1,3) +v s = 30v 0 +v s - 1.5 v cmrr common mode rejection ratio (1) dc, v cm = 0v to (+v s - 1.5v) 60 70 db 60 db output characteristics v oh output voltage swing, high (1) +v s = 30v, r l = 2k 26 v 26 v +v s = 30v, r l = 10k 27 28 v 27 v
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 5 electrical characteristics continued t a = 25c (if bold , t a = -40 to +85c), v s = +5v, -v s = gnd, r f = r g =2k, r l = 2k to v s /2, g = 2; unless otherwise noted. symbol parameter conditions min typ max units v ol output voltage swing, low (1) +v s = 5v, r l = 10k 5 20 mv 30 mv i source output current, sourcing (1) v in+ = 1v, v in- = 0v, +v s = 15v, v out = 2v 20 40 ma 20 i sink output current, sinking (1) v in+ = 0v, v in- = 1v, +v s = 15v, v out = 2v 10 15 ma 5 v in+ = 0v, v in- = 1v, +v s = 15v, v out = 0.2v 12 50 a i sc short circuit output current (1) +v s = 15v 40 60 ma notes: 1. 100% tested at 25c. (limits over the full temperature range are guaranteed by design.) 2. the input common mode voltage of either input signal voltage should be kept > 0.3v at 25c. the upper end of the common-mode voltage range is +v s - 1.5v at 25c, but either or both inputs can go to +36v without damages, independent of the magnitude of v s .
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 6 typical performance characteristics t a = 25c, +v s = 30v, -v s = gnd, r f = r g =2k, r l = 2k, g = 2; unless otherwise noted. frequency response vs. v out -3db bandwidth vs. v out frequency response vs. c l frequency response vs. r l non-inverting frequency response inverting frequency response - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) g = 1 r f = 0 g = 2 g = 5 g = 10 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) c l = 10nf r s = 0 c l = 5nf r s = 0 c l = 1nf r s = 0 c l = 100pf r s = 0 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) r l = 1k v out = 0.2v pp r l = 2k r l = 5k r l = 10k - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) vout = 2vpp vout = 4vpp 0 100 200 300 400 500 0.0 1.0 2.0 3.0 4.0 - 3db bandwidth (khz) v out (v pp )
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 7 typical performance characteristics t a = 25c, +v s = 30v, -v s = gnd, r f = r g =2k, r l = 2k, g = 2; unless otherwise noted. frequency response vs. v out at v s = 5v -3db bandwidth vs. v out at v s = 5v frequency response vs. c l at v s = 5v frequency response vs. r l at v s = 5v non-inverting frequency response at v s = 5v inverting frequency response at v s = 5v - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) g = 1 r f = 0 g = 2 g = 5 g = 10 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) c l = 10nf r s = 0 c l = 5nf r s = 0 c l = 1nf r s = 0 c l = 100pf r s = 0 v out = 0.2v pp - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) r l = 1k v out = 0.2v pp r l = 2k r l = 5k r l = 10k - 25 - 20 - 15 - 10 - 5 0 5 0.01 0.1 1 10 normalized gain (db) frequency (mhz) vout = 1vpp vout = 2vpp 0 50 100 150 200 250 300 350 400 0.0 0.5 1.0 1.5 2.0 - 3db bandwidth (khz) v out (v pp )
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 8 typical performance characteristics - continued t a = 25c, +v s = 30v, -v s = gnd, r f = r g =2k, r l = 2k, g = 2; unless otherwise noted. supply current vs. supply voltage input voltage range vs. power supply small signal pulse response at v s = 5v large signal pulse response at v s = 5v small signal pulse response large signal pulse response 2.35 2.40 2.45 2.50 2.55 2.60 2.65 0 10 20 30 40 50 output voltage (v) time (us) 0.00 1.00 2.00 3.00 4.00 5.00 0 10 20 30 40 50 output voltage (v) time (us) 2.35 2.40 2.45 2.50 2.55 2.60 2.65 0 10 20 30 40 50 output voltage (v) time (us) 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0 10 20 30 40 50 output voltage (v) time (us) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 5 10 15 20 25 30 35 40 supply current (ma) supply voltage (v) clc4050 clc2050 CLC1050 v out = 0.2v pp 0 5 10 15 0 5 10 15 input voltage (+/ - vdc) power supply voltage (+/ - vdc) negative positive
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 9 typical performance characteristics - continued t a = 25c, +v s = 30v, -v s = gnd, r f = r g =2k, r l = 2k, g = 2; unless otherwise noted. functional block diagram voltage gain vs. supply voltage input current vs. temperature 60 75 90 105 120 0 8 16 24 32 40 voltage gain (db) power supply voltage (v) r l =2k r l =20k v out = 0.2v pp 0 2 4 6 8 10 12 14 16 18 20 - 50 - 25 0 25 50 75 100 125 input current (na) temperature ( c) q 2 q 4 q 3 q 1 q 8 q 9 q10 q11 50a 100a 6a 4a q 5 q 6 q13 r s c q 7 + ? o utput q12 v c c c c i nputs
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 10 application information basic operation figures 1, 2, and 3 illustrate typical circuit confgurations for non-inverting, inverting, and unity gain topologies for dual supply applications. they show the recommended bypass capacitor values and overall closed loop gain equations. + - r f 0.1f 6.8f output g = 1 + ( r f /r g ) input +v s -v s r g 0.1f 6.8f r l figure 1. typical non-inverting gain circuit figure 2. typical inverting gain circuit + - 0.1f 6.8f output g = 1 input +v s -v s 0.1f 6.8f r l figure 3. unity gain circuit power dissipation power dissipation should not be a factor when operating under the stated 2k ohm load condition. however, ap - plications with low impedance, dc coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operat - ing range. maximum power levels are set by the absolute maximum junction rating of 150c. to calculate the junction tem - perature, the package thermal resistance value theta ja (? ja ) is used along with the total die power dissipation. t junction = t ambient + (? ja p d ) where t ambient is the temperature of the working environment. in order to determine p d , the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. p d = p supply - p load supply power is calculated by the standard power equa - tion. p supply = v supply i rms supply v supply = v s+ - v s- power delivered to a purely resistive load is: p load = ((v load ) rms 2 )/rload eff the effective load resistor (rload eff ) will need to include the effect of the feedback network. for instance, rload eff in fgure 3 would be calculated as: r l || (r f + r g ) these measurements are basic and are relatively easy to perform with standard lab equipment. for design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. here, p d can be found from p d = p quiescent + p dynamic - p load quiescent power can be derived from the specifed i s val - ues along with known supply voltage, v supply . load power can be calculated as above with the desired signal ampli - tudes using: + - r f 0.1f 6.8f output g = - ( r f /r g ) for optimum input offset voltage set r 1 = r f || r g input +v s -v s 0.1f 6.8f r l r g r 1
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 11 (v load ) rms = v peak / 2 ( i load ) rms = ( v load ) rms / rload eff the dynamic power is focused primarily within the output stage driving the load. this value can be calculated as: p dynamic = (v s+ - v load ) rms ( i load ) rms assuming the load is referenced in the middle of the pow - er rails or v supply /2. figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the pack - ages available. 0 0.5 1 1.5 2 2.5 - 40 - 20 0 20 40 60 80 maximum power dissipation (w) ambient temperature ( c) sot23 - 6 sot23 - 5 soic - 16 figure 4. maximum power derating driving capacitive loads increased phase delay at the output due to capacitive load - ing can cause ringing, peaking in the frequency response, and possible unstable behavior. use a series resistance, r s , between the amplifer and the load to help improve stability and settling performance. refer to figure 5. + - r f input output r g r s c l r l figure 5. addition of r s for driving capacitive loads table 1 provides the recommended r s for various capaci - tive loads. the recommended r s values result in <=1db peaking in the frequency response. the frequency re - sponse vs. c l plot, on page 6, illustrates the response of the clcx050. c l (pf) r s () -3db bw (khz) 1nf 0 485 5nf 0 390 10nf 0 260 100 0 440 table 1: recommended r s vs. c l for a given load capacitance, adjust r s to optimize the tradeoff between settling time and bandwidth. in general, reducing r s will increase bandwidth at the expense of ad - ditional overshoot and ringing. overdrive recovery an overdrive condition is defned as the point when ei - ther one of the inputs or the output exceed their specifed voltage range. overdrive recovery is the time needed for the amplifer to return to its normal or linear operating point. the recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. the clcx050 will typically recover in less than 30ns from an overdrive condition. figure 6 shows the CLC1050 in an overdriven condition. figure 6. overdrive recovery - 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 - 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 0 20 40 60 80 100 output voltage (v) input voltage (v) time (us) output input v in = 1.25v pp g = 5
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 12 layout considerations general layout and supply bypassing play major roles in high frequency performance. c adeka has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. follow the steps below as a basis for high frequency layout: ? include 6.8f and 0.1f ceramic capacitors for power supply decoupling ? place the 6.8f capacitor within 0.75 inches of the power pin ? place the 0.1f capacitor within 0.1 inches of the power pin ? remove the ground plane under and around the part, especially near the input and output pins to reduce para - sitic capacitance ? minimize all trace lengths to reduce series inductances refer to the evaluation board layouts below for more in - formation. evaluation board information the following evaluation boards are available to aid in the testing and layout of these devices: evaluation board # products ceb002 CLC1050 ceb006 clc2050 ceb018 clc4050 evaluation board schematics evaluation board schematics and layouts are shown in fig - ures 7-14. these evaluation boards are built for dual- sup - ply operation. follow these steps to use the board in a single-supply application: 1. short -vs to ground. 2. use c3 and c4, if the -v s pin of the amplifer is not directly connected to the ground plane. figure 7. ceb002 schematic figure 8. ceb002 top view
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 13 figure 9. ceb002 bottom view figure 10. ceb006 schematic figure 11. ceb006 top view figure 12. ceb006 bottom view
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 14 figure 13. ceb018 schematic figure 14 ceb018 top view figure 15. ceb018 bottom view typical applications a c line s m p s r 2 curren t sense r 7 r 8 ba t t e r y p a c k r 4 r 3 a z 4 3 1 r 5 r 1 o p t o isolato r v c c g n d + ? 1/ 2 clcx050 v c c g n d + ? 1/ 2 clcx050 r 6 figure 16. battery charger
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 15 r 1 9 10 k v o r 2 1 00 k r3 9 1 k +v i n v c c r l 1 / 2 clcx050 ? + figure 17. power amplifer v o r 5 1 00 k r 1 1 0 0 k r 2 1 0 0 k r 3 1 0 0 k r 4 1 0 0 k r 6 1 0 0 k + v 1 + v 2 + v 3 + v 4 1 / 2 clcx050 + ? figure 18. dc summing amplifer v cc r b 6.2k r l 10k r 1 10 0 k r 2 1m r 4 100k c 1 0.1f c 2 10f r3 1m r5 100k c in c o v o a v = 1 + r2/r1 a v = 11 (as shown) ? + ac 1/ 2 clcx050 figure 19. ac-coupled non-inverting amplifer v cc r4 3k r3 2k + ? 2 v + ? 2 v i 1 i 2 1ma 1/2 clcx050 r1 2k r2 ? + figure 20. fixed current sources r1 1m r2 100k r3 100k r5 100k r4 100k v o v cc 1 / 2 clcx050 0 . 0 0 1f ? + figure 21. pulse generator v o v in 1/2 clcx050 c1 0.01f c2 0.01f r3 100k r1 16k r2 16k r4 100k f o f o =1khz q=1 a v =2 v o 0 + ? figure 22. dc-coupled low-pass active filter
data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a ?2007-2009 cadeka microcircuits llc www.cadeka.com 16 mechanical dimensions sot23-5 package soic-8 package
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear, the comlinear logo design, and arctic are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2007-2009 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) data sheet c omlinear CLC1050, clc2050, clc4050 low power, 3v to 36v, single, dual, quad amplifers rev 1a mechanical dimensions continued soic-14 package a m p l i f y t h e h u m a n e x p e r i e n c e

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